FBE-ASIC microelectronics experts

Dr. Peter Sänger

Key points:
  • Digital and FPGA systems expert
  • More than 20 years experience
Special experience (design flows):
  • Analysis and review of specifications
  • Designing efficient architecture from specification
  • Implementation of logic blocks in VHDL for synthesis
  • Designing efficient test benches in VHDL (behaviour)
  • Design verification by simulation (functional/random)
  • Using code coverage to increase verification quality
  • Building constrains and synthesize the design
  • Using static timing analysis and gate level simulation to verify the synthesis step
  • Scan path insertion for ASIC designs
  • Floor planning and building physical constraints for Place and Route step
  • Start up and hardware verification of the design on evaluation boards or PCBs
Special experience (hardware, logic blocks):
  • Bus systems (AMBA AHB, Wishbone, PCI, OPB, PLB, SPI and I²C)
  • Protocols (HDLC, PPP, HSSL, ATM, LTE, Ethernet 10/100/1000, IPv4 and IPv6, RS232)
  • Interfaces (SDR-, DDR- and QDR-RAM, DSP-EMIF, DSP-HPI, ATM Utopia level 2, MII
  • Signal processing (FIR-, Polyphase-, Decimation-, Interpolation-filter and filter arrays, down converter, vector-matrix-multiply with complex numbers, FFT, IFFT
  • Embedded processors (PowerPC 405, Microblaze, Picoblaze)
  • Encryption/Decryption (AES-128, -192, -256)
Peter Sänger