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last update : June 2017
Verification
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Verification
Verification is more than simulation
Using our experience of virtually all state-of-the-art verification methodologies from more than 20 verification projects, we will also find the optimum method to verify your design. We have expertise in the following areas:
Small VHDL / Verilog based solutions with no or almost no abstraction layer for test writing
Constrained random and coverage driven verification environments in SystemVerilog (OVM), Specman-e and SystemC for IP and system level verification
Matrix driven verification using verification plans and verification-management tools from Cadence and Mentor Graphics
MatLab based verification environments for signal processing systems
Automated verification environments for SoC-families; setup generation for SOC derivatives virtually within minutes !
Formal verification using SVA and PSL for property definitions
FBE-ASIC is verification partner of Cadence and Mentor Graphics.
Examples:
Verilog
SystemVerilog(OVM)
Mixed-Signal
SystemC/SV based
SoC Automation
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